9DBL0255NLGI

9DBL0255NLGI is a 2 output 3.3V PCIe Gen1–5 clock fanout buffer with LOS. This have an open drain loss of signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements automatic clock parking (ACP) to cleanly park the outputs low/low when the input clock goes away. The devices implement several additional features to aid robust designs. Flexible power sequencing (FPS) ensures well-defined behavior under various power up scenarios, while power down tolerant (PDT) ESD protection allows input pins to be driven before VDD is applied. The 9DBL0255/9DBL0455 are spread-spectrum compatible and provide direct connection to 85Ω transmission lines. It can also be used in 100 ohm environments with simple external resistors. Typical application includes PCIe clock distribution in is PCIe riser cards, NVME eSSD and JBOD, high-performance computing and accelerators.

• 3 × 3mm, 16-VFQFPN package, 2 output, common clocked
• Independent reference clock (SRIS, SRnS), additive phase jitter 46fs RMS (typ) at 156.25MHz
• FPS: VDD may be applied with floating input clock or input clock may be driven before VDD is applied
• Easy AC-coupling to other logic families
• 85ohm loads require 0 termination resistors
• 100ohm loads require only 2 series resistors per output
• OE# pin for each output, spread-spectrum tolerant
• Input-to-output delay <lt/> 3ns, output-to-output skew <lt/> 50ps
• Additive phase jitter <lt/> 15fs RMS for PCIe Gen5
• Industrial temperature range from -40°C to +85°C