SPC5644AF0MLU1

SPC5644AF0MLU1 is a microcontroller’s e200z4 host processor core built on Power Architecture® technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP). The MPC5644A has two levels of memory hierarchy consisting of 8KB of instruction cache, backed by 192KB on-chip SRAM and 4MB of internal flash memory with ECC and read while write (RWW). The MPC5644A includes an external bus interface, and also a calibration bus that is only accessible when using the Vertical Calibration System.

• Automotive qualified
• Variable length instruction encoding (VLE) and superscalar architecture with 2 execution units
• 24 entry MMU, 5 x 4 crossbar switch (XBAR), 14 + 3 KB eTPU code and data RAM
• Fail-safe protection (16-entry MPU, CRC unit with 3 sub-modules, junction temperature sensor)
• Interrupts: configurable interrupt controller (with NMI) and 64-channel DMA
• On-chip CAN/SCI/FlexRay bootstrap loader with Boot Assist Module (BAM)
• Up to 120 general purpose I/O lines: Individually programmable as input, output or special function
• 5V single supply with external ballast and multiple external supply: 5 V, 3.3V and 1.2V
• Development Trigger Semaphore (DTS)
• 176 pin LQFP package, temperature range from -40°C to 125°C and 150MHz speed