74LV165APW,118

74LV165APW,118 is an 8bit parallel-in/serial-out shift register with complementary serial outputs (Q7 and active low Q7) available from the last stage. When the parallel-load input (active low PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input active low PL is HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage.

• Wide supply voltage range from 2V to 5.5V
• Synchronous parallel-to-serial applications
• Synchronous serial input for easy expansion
• Latch-up performance exceeds 250mA
• CMOS LOW power consumption
• 5.5V tolerant inputs/outputs
• Direct interface with TTL levels (2.7V to 3.6V)
• Power-down mode
• 16 pin TSSOP package
• Temperature ranges from -40°C to +85°C