74HC595D,118

74HC595D,118 is a 8-bit serial-in, serial or parallel-out shift register with output latches 3-state. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset (active-low) MR input. A LOW on (active-low)MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (active-low) (OE) is LOW. A HIGH on (active-low) OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. Suitable for serial-to-parallel data conversion, remote control holding register applications.

• 8 bit serial input
• 8 bit serial or parallel output
• Storage register with 3 state outputs
• Shift register with direct clear
• 100MHz typ. shift out frequency and 108MHz max frequency at VCC = 6V
• Wide supply voltage range from 2V to 6V
• CMOS low power dissipation
• High noise immunity
• 16 pin SO package
• Temperature range from -40°C to +125°C