74AUP2G04GW,125

74AUP2G04GW,125 is a dual inverter. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standards (JESD8-12 (0.8V to 1.3V), JESD8-11 (0.9V to 1.65V), JESD8-7 (1.2V to 1.95V), JESD8-5 (1.8V to 2.7V), JESD8-B (2.7V to 3.6V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• High noise immunity, inputs accept voltages upto 3.6V
• Latch-up performance exceeds 100mA per JESD 78 Class II
• Low noise overshoot and undershoot <lt/> 10% of VCC
• IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.1μA maximum at (VI=GND to 3.6V;VCC = 0V to 3.6V, Tamb = 25°C)
• Supply current is 0.5μA maximum at (VI=GND or VCC;IO = 0A;VCC = 0.8V to 3.6V, Tamb = 25°C)
• Input capacitance is 0.8pF typical at (VCC = 0V to 3.6V;VI= GND or VCC, Tamb = 25°C)
• Propagation delay is 16ns typical at (VCC = 0.8V, Tamb = 25°C)
• Operating temperature range from -40°C to +125°C
• TSSOP6 package

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