MT53E256M32D1KS-046 IT:L

MT53E256M32D1KS-046 IT:L is a mobile LPDDR4 SDRAM. The 8Gb mobile low-power DDR4 SDRAM with low VDDQ (LPDDR4X) is a high-speed, CMOS dynamic random-access memory device. This device is internally configured with 2 channel ×16 I/O, having 8-banks per channel. The LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture. A write/read access consists of a single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n-bit-wide data transfers at the I/O pins. Read and write accesses to the device are burst-oriented. Accesses start at a selected column address and continue for a programmed number of columns in a programmed sequence.

• Frequency range: 2133–10MHz (data rate range per pin: 4266–20Mb/s)
• 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL), programmable and on-the-fly burst lengths (BL=16,32)
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• On-chip temperature sensor to control self refresh rate, partial-array self refresh (PASR)
• Selectable output drive strength (DS), clock-stop capability
• Device configuration: 256M32 x 1 die in package
• 468ps at RL = 36/40 speed grade, cycle time
• 200-ball VFBGA package, -40°C to +95°C temperature range