MT46H32M32LFB5-5 IT:B

MT46H32M32LFB5-5 IT:B is a mobile low-power DDR SDRAM. It is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks are organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks are organized as 8192 rows by 1024 columns by 32 bits.

• Operating voltage range is 1.8V, deep power-down (DPD)
• 32Meg x 32 configuration, clock stop capability
• Packaging style is 90-ball (8mm x 13mm) VFBGA, “green”
• Timing (cycle time) is 5ns at CL = 3 (200 MHz), JEDEC-standard addressing
• Industrial operating temperature range is –40°C to +85°C, second generation
• Clock rate is 200MHz, bidirectional data strobe per byte of data (DQS)
• Differential clock inputs (CK and CK#), commands entered on each positive CK edge
• DQS edge-aligned with data for READs, centeraligned with data for WRITEs
• Concurrent auto precharge option is supported, auto refresh and self refresh modes
• Temperature-compensated self refresh (TCSR), partial-array self refresh (PASR)