ADF4001BRUZ

ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13bit N counter. In addition, the 14bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation. Typical applications are clock generation, low frequency PLLs, low jitter clock source, clock smoothing, frequency translation, SONET, ATM, ADM, DSLAM, SDM.

• Separate charge pump supply (VP) allows extended
• Programmable charge pump currents, 3-wire serial interface
• Hardware and software power-down mode, analogue and digital lock detect
• Hardware compatible to the ADF4110/ADF4111/ADF4112/ADF4113
• Ultralow phase noise, tuning voltage in 5V systems
• 2.7V to 5.5V power supply ((AVDD=DVDD=3V±10%, 5V±10%; AVDD ≤ VP ≤ 6.0 V; AGND=DGND =CPGND=0V)
• 200MHz bandwidth
• Typical operating current is 4.5mA
• 16-lead thin shrink small outline package
• Temperature rating range from -40°C to +85°C

บันทึก

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party