AD9571ACPZLVD

AD9571 provides a multioutput Ethernet clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage controlled oscillator, and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25MHz can be locked to the input reference. Application includes Ethernet line cards, switches, and routers, SCSI, SATA, and PCI-express, PCI support included, low jitter, low phase noise clock generation.

• Fully integrated VCO/PLL core
• Jitter integration bandwidth is 0.17ps rms (typ, 156.25MHz, VS = 3.3V, TA = 25°C)
• Input crystal or clock frequency of 25MHz
• Choice of LVPECL or LVDS output format, integrated loop filter
• 6 copies of reference clock output, rates configured via strapping pins
• Phase noise characteristics is -120dBc/Hz (typ, 33.33MHz output disabled, TA = 25°C, at 1KHz)
• Input frequency is 25MHz (typ, VS = 3.3V ± 10%, TA = 25°C)
• Output frequency is 156.25MHz (max, VS = 3.3V ± 10%, TA = 25°C)
• Duty cycle range from 45 to 55% (VS = 3.3V ± 10%, TA = 25°C)
• 40 lead LFCSP-WQ package, operating temperature range from -40°C to +85°C

บันทึก

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