AS4C512M16D3LA-10BCN

AS4C512M16D3LA-10BCN is a 8Gbit DDR3L SDRAM. Read and write operations to the DDR3 SDRAM are burst-oriented, start at a selected location, and continue for a burst length of four or eight in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10/AP), and select BC4 or BL8 mode “on the fly” (via A12) if enabled in the mode register.

• Double-data-rate architecture; two data transfers per clock cycle, 933MHz maximum clock
• The high-speed data transfer is realized by the 8bits prefetch pipelined architecture
• DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
• Differential clock inputs (CK and active-low CK), SRT range : normal/extended
• DLL aligns DQ and DQS transitions with CK transitions, eight internal banks for concurrent operation
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• On-die termination (ODT) for better signal quality, synchronous, dynamic, asynchronous ODT
• Multi purpose register (MPR) for pre-defined pattern read out, 1866Mbps data rate
• ZQ calibration for DQ drive and ODT, programmable output driver impedance control
• 96-ball FBGA package, commercial temperature range from 0°C to 95°C