AS4C128M8D3LC-12BCN

AS4C128M8D3LC-12BCN 1Gb double-data-rate-3L (DDR3L) DRAM is a double data rate architecture to achieve high-speed operation. It is internally configured as an eight-bank DRAM. The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank devices. This synchronous device achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source-synchronous fashion.

• JEDEC standard compliant, supports JEDEC clock jitter specification
• Power supplies: VDD and VDDQ=1.35V (1.283 to 1.45V), backward compatible to VDD and VDDQ=1.5±0.075V
• Fully synchronous operation, fast clock rate: 800MHz, differential clock, CK and CK#
• Bidirectional differential data strobe, DQS and DQS#, 8 internal banks for concurrent operation
• 8n-bit prefetch architecture, pipelined internal architecture
• Precharge and active power down, programmable mode and extended mode registers
• Additive latency: 0, CL-1, CL-2, burst type: sequential/interleave, output driver impedance control
• Auto refresh and self refresh, write levelling, ZQ calibration, dynamic ODT (Rtt-Nom and Rtt-WR)
• 128M x 8 org, 78-ball FBGA package
• Commercial temperature range from 0°C to 95°C