AS4C128M16MD4V-062BAN

AS4C128M16MD4V-062BAN is a LPDDR4X SDRAM. It is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

• 128Mx16 org, 1600MHz maximum clock frequency
• LVSTL (low voltage swing terminated logic) I/O interface
• Selectable output drive strength (DS), 16-bit pre-fetch DDR data bus
• Single data rate (multiple cycles) command/address bus
• Bidirectional/differential data strobe per byte of data (DQS, DQS)
• DMI pin support for write data masking and DBI functionality
• Programmable READ and WRITE latencies (RL/WL)
• Support non-target DRAM ODT control, on-chip temperature sensor to control self refresh rate
• On-chip temperature sensor whose status can be read from MR4
• Automotive temperature range from -40°C to 105°C, 200-ball FBGA package