IS43TR16256BL-125KBL

IS43TR16256BL-125KBL is a 1600MT/s 256Mx16 4Gb DDR3 SDRAM. The memory controller initiates levelling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write levelling mode, the DQ pins are in undefined driving mode. During write levelling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to exit write levelling mode. The controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller.

• Standard voltage is VDD and VDDQ = 1.5V ± 0.075V
• High-speed data transfer rates with system frequency up to 1066MHz
• 8 internal banks for concurrent operation, 8n-bit pre-fetch architecture
• Programmable CAS latency, programmable additive latency: 0, CL-1, CL-2
• Programmable CAS WRITE latency (CWL) based on tCK, programmable burst length: 4 and 8
• Programmable burst sequence: sequential or interleave, BL switch on the fly
• Auto self refresh(ASR), self refresh temperature (SRT)
• Partial array self-refresh, the asynchronous RESET pin, write levelling
• 96-ball BGA package
• Industrial rating range from -40°C ≤ TC ≤ 95°C