8A34004E-000NBG

8A34004E-000NBG is a synchronization management unit (PMU). It provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, digitally controlled oscillators (DCO), or digital phase lock loops (DPLL). The filter/servo software is designed to suppress the affects of Packet Delay Variation (PDV) on packet based timing signals – it can be used with protocol stacks for IEEE 1588 or other packet-based timing protocols. Typical application includes core and access IP switches / routers, synchronous Ethernet equipment, telecom boundary clocks (T-BCs) and T-TSCs according to ITU-T G.8273.2, 10Gb, 40Gb, and 100Gb Ethernet interfaces, central office timing source and distribution, wireless infrastructure for 4.5G and 5G network equipment.

• 7 × 7 × 0.75 mm 48-VFQFPN with 5.65mm ePAD package
• Two independent timing channels, supports 1MHz I²C or 50MHz SPI serial processor ports
• DPLLs generate telecom compliant clocks
• Switching between DPLL and DCO modes is hitless and dynamic
• Each FOD supports output phase tuning with 1ps resolution
• 4 differential / 8 LVCMOS outputs, frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
• Independent output voltages of 3.3V, 2.5V, or 1.8V, 2 differential / 4 single-ended clock inputs
• Support frequencies from 0.5Hz to 1GHz, any input can be mapped to any or all of the timing channels
• Redundant inputs frequency independent of each other, 1149.1 JTAG boundary scan
• Temperature range from -40° to +85°C