S25FL128LAGNFM010

S25FL128LAGNFM010 is a FL-L flash non-volatile memory using floating gate technology, 65-nm process lithography. The FL-L family connects to a host system via a serial peripheral interface (SPI). In addition, there are double data rate read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a page programming buffer that allows up to 256bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block sector, 64KB block sector, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.

• 128Mb density, 65-nm floating gate process technology
• 133MHz DDR speed, 8-contact WSON package type
• Temperature range from -40°C to +125°C (automotive, AEC-Q100 grade 1)
• SPI with multi-I/O, clock polarity and phase modes 0 and 3
• Commands, normal, fast, dual I/O, quad I/O, dualO, quadO, DDR quad I/O
• Modes, burst wrap, continuous (XIP), QPI, program suspend and resume
• Serial flash discoverable parameters (SFDP) for configuration information
• Program architecture, 256bytes page programming buffer
• 100000 program-erase cycles (minimum), 20 year data retention (minimum)